View FA7711V_4528685.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

an-060e rev.1.0 jun-2010 1 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ fuji power supply control ic dc/dc power supply control ic FA7711V application note june-2010 fuji electric systems co.,ltd.
an-060e rev.1.0 jun-2010 2 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 1. this data book contains the product specifications, characteristics, data, materi als, and structures as of june 2010. the contents are subject to change without notice for specification changes or other reasons. when using a product listed in this data book , be sure to obtain the latest specifications. 2. all applications described in this data book exemp lify the use of fuji's products for your reference only. no right or license, either express or implied, under any patent, copyrigh t, trade secret or other intellectual property right owned by fuji electric co., ltd. is (or shall be deemed) granted. fuji makes no representation or warranty, whether express or im plied, relating to the infringement or alleged infringement of other's intellectual property rights , which may arise from the use of the applications, described herein. 3. although fuji electric is enhancing product quality and reliability, a small percentage of semiconductor products may become faulty. when using fuji electric semiconductor products in your equipment, you are requested to take adequate safety measures to prev ent the equipment from causing a physical injury, fire, or other problem if any of the pr oducts become faulty. it is recommended to make your design fail-safe, flame retardant, and free of malfunction. 4.the products introduced in this data book are intended for use in the following electronic and electrical equipment, which has normal reliability requirements. ? computers ? oa equipment ? communications equipment (pin devices) ? measurement equipment ? machine tools ? audiovisual equipment ? electrical home appliances ? personal equipment ? industrial robots etc. 5.if you need to use a product in this data book for equipment requiring higher re liability than normal, such as for the equipment listed below, it is imperative to contact fuji electric to obtain prior approval. when using these products for such equipment, take adeq uate measures such as a backup system to prevent the equipment from malfunctioning even if a fuji's pr oduct incorporated in the equipment becomes faulty. ? transportation equipment (mounted on cars and ships) ? trunk communications equipment ? traffic-signal control equipment ? gas le akage detectors with an auto-shut-off feature ? emergency equipment for responding to disasters and anti-burglary devices ? safety devices 6. do not use products in this data book for the equipment requiring strict reliability such as (without limitation) ? space equipment ? aeronautic equipment ? atomic control equipment ? submarine repeater equipment ? medical equipment 7. copyright ? 1995 by fuji electric co., ltd. all right s reserved. no part of this data book may be reproduced in any form or by any means wi thout the express permission of fuji electric. 8. if you have any question about any portion in this da ta book, ask fuji electric or its sales agents before using the product. neither fuji nor its agents shall be liable for any injury caused by any use of the products not in accordance with instructions set forth herein. warning
an-060e rev.1.0 jun-2010 3 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ contents 1. description 4 2. features 4 3. outline 4 4. block diagram 5 5. pin assignment 5 6. ratings and c haracteristics 6 7. characteristics curves 10 8. description of each circ uit 15 9. design ad vice 18 10. applicati on circui t 25 note ? parts tolerance and characteristics are not defined in all application described in this data book. when design an actual circuit for a product, you must determi ne parts tolerances and characteristics for safe and stable operation.
an-060e rev.1.0 jun-2010 4 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 1. description FA7711V is a pwm type dc-to-dc converter control ic with 3ch outputs that c an directly drive power mosfets. cmos devices with high breakdown voltage ar e used in this ic and low power consumption is achieved. this ic is suitable for very small dc-to- dc converters because of their small and thin package (1.2mm max.), and high frequency operation (to 800khz). you can select pch or nch of mosfets driven, and design any topology of dc-to-dc converter circuit like a buck, a boost, a inverting, a fly-back, or a forward. 2. features ? mosfet direct driving ( note : this function is available only for that vcc is below 20v ) ? selectable output stage for pch/nch mosfet on each channel ? low operating current by cmos process: 7ma (typ.) ? 3ch pwm control ic ? high frequency operation: 200khz to 800khz ? simple setting of operation frequency by timing resistor ? soft start function at each channel ? adjustable maximum duty cycle at each channel ? built-in under voltage lockout ? high accuracy reference voltage: v ref : 3.7v1% ? adjustable built-in timer latch for short-circuit protection ? thin and small package: tssop-24 3. outline 0.100.05 24 #1 1.00.1 0.17 5.60.1 h 7.80.1 02 1d 0 12 711v 7 7.60.2 lot.no. 0.65 0.270.02 1.20 max typ. unit mm
an-060e rev.1.0 jun-2010 5 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 4. block diagram reference voltge oscillator timer latch er.amp.1 er.amp.2 comp.1 comp.2 n/p ch drive fb voltage dtection p ch drive vref ? vcc ? cs3 ? out1 ? out2 sel2 gnd cp in1- fb1 ? in2- ? fb2 rt er.amp.3 n/p ch drive comp.3 soft start pgnd ? cs2 ? cs1 ? out3 sel3 in1+ pgnd pvcc pgnd pvcc pgnd pvcc ? pvcc pvcc pgnd in3+ 24 in3- 23 fb3 22 in2+ 21 5. pin assignment pin no. pin symbol description 1 cp timer latched short circuit protection 2 rt oscillator timing resistor 3 sel3 selection of type of driven mosfet(out3) 4 vref reference voltage 5 sel2 selection of type of driven mosfet(out2) 6 in1+ ch.1 non-inverting input to error amplifier 7 in1- ch.1 inverting input to error amplifier 8 fb1 ch.1 output of error amplifier 9 gnd ground 10 pgnd ground for driver 11 cs1 soft start for ch.1 12 out1 ch.1 output 13 out2 ch.2 output 14 cs2 soft start for ch.2 15 out3 ch.3 output 16 cs3 soft start for ch.3 17 pvcc power supply for driver 18 vcc power supply 19 fb2 ch.2 output of error amplifier 20 in2- ch.2 inverting input to error amplifier 21 in2+ ch.2 non-inverting input to error amplifier 22 fb3 ch.3 output of error amplifier 23 in3- ch.3 inverting input to error amplifier 24 in3+ ch.3 non-inverting input to error amplifier
an-060e rev.1.0 jun-2010 6 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 6. ratings and characteristics (1)absolute maximum ratings item symbol conditions ratings units power supply voltage (vcc,pvcc pin) v cc 30 v sel2,sel3 pin voltage v sel - 0.3 to 5.0 v fb1,in1-,in1+,fb2,in 2-,in2+,fb3,in3-,i n3+ pin voltage v ea_in - 0.3 to 5.0 v cs1,cs2,cs3,cp,rt,vref pin voltage v ctr_in - 0.3 to 5.0 v out1/2/3 pin source current i out- - 800(peak) ma out1/2/3 pin sink current i out+ +800(peak) ma out1/2/3 pin source current i out- - 50(continuous) ma out1/2/3 pin sink current i out+ +50(continuous) ma power dissipation pd ta Q 25 800 mw operating junction temperature t j +125 operating ambient temperature t opr - 20 to +85 storage temperature t stg - 40 to +125 *1: ic is soldered on glass-epoxy printed board (40mm 80mm 1.6mm). derating factor ta R 25 :8mw/ maximum power dissipation curve 0 200 400 600 800 1000 -20 0 20 40 60 80 100 120 140 ambient temperature [ ] maximum power dissipation [mw] thermal resistance: j-c (junction to case)=70 /w ic is soldered on glass-epoxy printed board (40mm 80mm 1.6mm). (2)recommended operating conditions item symbol condition min. typ. max. unit power supply voltage (vcc) v cc 4.5 28 v power supply voltage (pvcc) *2 v pcc 4.5 28 v cs1,cs2,cs3,cp pin voltage v ctr_in 0.0 4.1 v sel2,sel3 pin voltage v sel_in 0.0 4.1 v in1-,in1+,in2-,in 2+,in3-,in3+ pin voltage v ea_in 0.0 4.1 v oscillation frequency f osc 200 800 khz vref pin capacitance c ref 1.0 4.7 f vcc pin capacitance c vcc 1.0 f pvcc pin capacitance c pvcc 1.0 f cs1,cs3 pin capacitance c cs1 between cs1/3 and gnd 0.1 f cs2 pin capacitance c cs2 between cs2 and vref 0.1 f cp pin capacitance c cp between cp and gnd 0.01 f *2: apply the same voltage to vcc, pvcc pins.
an-060e rev.1.0 jun-2010 7 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ (3)electrical chracteristics ? the characteristics is ba sed on the condition of v cc =12v c ref =1.0 f r t =9.0k ? ta=+25 ,unless otherwise specified (1)refreence voltage section (vref pin) item symbol condition min. typ. max. unit reference voltage v ref 3.663 3.700 3.737 v line regulation v ref_line v cc =4.5 to 28v,i ref =0ma 8 25 mv i ref =0 to 7ma,v cc =8v to 28v - 20 - 5 mv load regulation v ref_load i ref =0 to 1ma,v cc =4.5v to 8v - 5 variation with temperature v ref_tc1 ta=- 20 to +85 0.5 % (2)oscillator section (rt pin) item symbol condition min. typ. max. unit oscillation frequency f osc r t =9.0k 500 560 620 khz line regulation f osc_line v cc =4.5 to 28v 1 5 % variation with temperature f osc_tc1 ta=- 20 to +85 3 % (3)error amplifier section (in1+ in1- fb1 in2+ in2- fb2 in3+ in3- fb3 pin) item symbol condition min. typ. max. unit input offset voltage v offset v in+ =1.8v in+ - in- D D 10 mv line regulation (input offset) v off_line v cc =4.5 to 28v 0 mv input current i in v in =0.0 to 5v 0 a common mode input voltage v com 0.5 2.7 v open loop gain a vo 70 db unity gain bandwidth f t 1.5 mhz output sink current i sifb v fb =0.5v,v in- =v ref ,v in+ =1.8v 1.9 2.7 3.5 ma output source current i sofb v fb =v ref - 0.5v,v in- =0v,v in+ =1.8v - 280 - 185 - 90 a (4)soft start section (cs1 cs2 cs3 pin) item symbol condition min. typ. max. unit v cs3d20n d uty3 =20%,v fb3 =2.8v 1.4 1.5 1.6 v threshold voltage (cs3) (driving nch-mosfet) v cs3d80n d uty3 =80%,v fb3 =2.8v 2.0 2.1 2.2 v v cs1/3d0p d uty1/3 =20%,v fb1/3 =2.8v 1.4 1.5 1.6 v threshold voltage (cs1/3) (driving pch-mosfet) v cs1/3d20p d uty1/3 =80%,v fb1/3 =2.8v 2.0 2.1 2.2 v v cs2d20n d uty2 =20%,v fb2 =0.8v 2.0 2.1 2.2 v threshold voltage (cs2) (driving nch-mosfet) v cs2d80n d uty2 =80%,v fb2 =0.8v 1.4 1.5 1.6 v v cs2d20p d uty2 =20%,v fb2 =0.8v 2.0 2.1 2.2 v threshold voltage (cs2) (driving pch-mosfet) v cs2d80p d uty2 =80%,v fb2 =0.8v 1.4 1.5 1.6 v
an-060e rev.1.0 jun-2010 8 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ (5)pulse width modulation section (fb1 fb2 fb3 pin) item symbol condition min. typ. max. unit v fb3d20n d uty3 =20%,v cs3 =v ref 1.5 v threshold voltage (fb3) (driving nch-mosfet) v fb3d80n d uty3 =80%,v cs3 =v ref 2.1 v v fb1/3d20p d uty1/3 =20%,v cs1/3 =v ref 1.5 v threshold voltage (fb1/3) (driving pch-mosfet) v fb1/3d80p d uty1/3 =80%,v cs1/3 =v ref 2.1 v v fb2d20n d uty2 =20%,v cs2 =0v 2.1 v threshold voltage (fb2) (driving nch-mosfet) v fb2d80n d uty2 =80%,v cs2 =0v 1.5 v v fb2d20p d uty2 =20%,v cs2 =0v 2.1 v threshold voltage (fb2) (driving pch-mosfet) v fb2d80p d uty2 =80%,v cs2 =0v 1.5 v (6)under voltage lockout section (vcc pin) item symbol condition min. typ. max. unit on threshold voltage of vcc v uvloon 2.6 3.3 4.0 v hysteresis voltage v uvlohys 0.1 v (7)timer latch protection section (cp pin) item symbol condition min. typ. max. unit threshold voltage of fb1 v thfb1on *7-1 2.8 3.0 3.2 v threshold voltage of fb2 v thfb2on *7-2 0.4 0.6 0.8 v threshold voltage of fb3 v thfb3on *7-3 2.8 3.0 3.2 v charge current of cp i cp v cp =0.5v,v fb1 =v ref - 0.5v - 3.5 - 2.5 - 1.5 a threshold voltage of cp v thcpon 2.8 3.0 3.2 v *7-1:the current source of the cp pin operates when the voltage of fb1 exceeds the threshold voltage as shown in the table *7-2:the current source of the cp pin operates when the voltage of fb2 fall below the threshold voltage as shown in the table *7-3:the current source of the cp pin operates when the voltage of fb3 exceeds the threshold voltage as shown in the table
an-060e rev.1.0 jun-2010 9 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ (8)output section (out1 out2 out3 sel2 sel3 pin) item symbol condition min. typ. max. unit high side on resistance r onhi i out =- 100ma 3 5 low side on resistance r onlo i out =+100ma 3 5 rise time (driving pch-mosfet) t risep 30 ns fall time (driving pch-mosfet) t fallp vcc- out:7 +2000pf *8-1 30 rise time (driving nch-mosfet) t risen 30 ns fall time (driving nch-mosfet) t falln out- gnd:7 +2000pf *8-2 30 sel2/3 pin voltage for driving nch-mosfet v seln 0.0 D 0.35 v sel2/3 pin voltage for driving pch-mosfet v selp v ref - 0.35 D v ref v (9)overall section item symbol condition min. typ. max. unit operating mode r t =9.0k 7 9 ma i ccop r t =5.7k 8 11 operating mode supply current i ccd100 latch mode 4 ma *8-1 *8-2 10% 50% 90% trise tfall
an-060e rev.1.0 jun-2010 10 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 7. characteristic curves timing resistor vs. oscillation frequency 0 100 200 300 400 500 600 700 800 900 0 5 10 15 20 25 30 timing resistor r t [k ? ] oscillation frequency [khz] oscillation frequency vs. ambient temperature 550 555 560 565 570 -50 -25 0 25 50 75 100 125 150 ambient temperatureta [ ] oscillation frequency [khz] reference voltage vs. ambient temperature 3.60 3.62 3.64 3.66 3.68 3.70 3.72 3.74 3.76 -50 -25 0 25 50 75 100 125 150 ambient temperature ta [ ] reference voltage v ref [v] i ref =0a reference voltage vs. load current 3.65 3.67 3.69 3.71 3.73 3.75 024681012 load current i ref [m a] reference voltage v ref [v] oscillation frequency vs. supply voltage 550 552 554 556 558 560 562 564 566 568 570 0 5 10 15 20 25 30 vcc [v] oscillation frequency [khz] reference voltage vs. supply voltage i ref = 0ma 3.680 3.685 3.690 3.695 3.700 3.705 3.710 3.715 3.720 0 5 10 15 20 25 30 supply voltage vcc [v] rerfernce voltage vref [v]
an-060e rev.1.0 jun-2010 11 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ fb pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.2 1.4 1.6 1.8 2.0 2.2 2.4 fb1 pin voltage [v] duty cycle [%] out1 focs=200khz focs=560khz focs=800khz fb pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.21.41.61.82.02.22.4 fb2 pin voltage [v] duty cycle [%] out2:pch driven focs=200khz focs=560khz focs=800khz fb pin voltage vs.duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.21.41.61.82.02.22.4 fb2 pin voltage [v] duty cycle [%] out2:nch driven focs=200khz focs=560khz focs=800khz fb pin voltage vs.duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.2 1.4 1.6 1.8 2.0 2.2 2.4 fb3 pin voltage [v] duty cycle [%] out3:pch driven focs=200khz focs=560khz focs=800khz fb pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.2 1.4 1.6 1.8 2.0 2.2 2.4 fb3 pin voltage [v] duty cycle [%] out3:nch driven focs=200khz focs=560khz focs=800khz
an-060e rev.1.0 jun-2010 12 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ cs pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.21.41.61.82.02.22.4 cs1 pin voltage [v] duty cycle [%] out1 focs=200khz focs=560khz focs=800khz cs pin volatege vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.21.41.61.82.02.22.4 cs2 pin voltage [v] duty cycle [%] out2:pch driven focs=200khz focs=560khz focs=800khz cs pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.21.41.61.82.02.22.4 cs2 pin voltage [v] duty cycle [%] out2:nch driven focs=200khz focs=560khz focs=800khz cs pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.2 1.4 1.6 1.8 2.0 2.2 2.4 cs3 pin voltage [v] duty cycle [%] out3:pch driven focs=200khz focs=560khz focs=800khz cs pin voltage vs. duty cycle 0 10 20 30 40 50 60 70 80 90 100 1.2 1.4 1.6 1.8 2.0 2.2 2.4 cs3 pin voltage [v] duty cycle [%] out3:nch driven focs=200khz focs=560khz focs=800khz
an-060e rev.1.0 jun-2010 13 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ cp pin charge current vs. ambient temperature -4.0 -3.5 -3.0 -2.5 -2.0 -1.5 -1.0 -50 -25 0 25 50 75 100 125 150 ambient temperature ta [ ] cp pin charge current [ a] cp pin threshold voltage vs. ambient temperature 2.90 2.95 3.00 3.05 3.10 -50 -25 0 25 50 75 100 125 150 ambient tenperature ta [ ] cp pin threshold voltage [v] fb1/3 pin threshold voltage vs. ambient temperature 2.90 2.95 3.00 3.05 3.10 -50 -25 0 25 50 75 100 125 150 ambient temperature ta [ ] fb1/3 pin threshold voltage [v] fb2 pin threshold voltage vs. ambient temperature 0.50 0.55 0.60 0.65 0.70 -50 -25 0 25 50 75 100 125 150 ambient temperature ta [ ] fb2 pin threshold voltage [v] uvlo threshold voltage vs. ambient temperature 3.00 3.10 3.20 3.30 3.40 3.50 3.60 -50 -25 0 25 50 75 100 125 150 ambient temperature ta [ ] uvlo threshold voltage [v] operationg mode supply current vs. supply voltage 0 2 4 6 8 10 12 14 16 0 5 10 15 20 25 30 35 supply voltage vcc [v] operating mode supply current [ma] f = 800khz f = 560khz f = 200khz
an-060e rev.1.0 jun-2010 14 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ out pin low side voltage vs.sink current 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.0 0.5 1.0 1.5 2.0 2.5 3.0 out pin voltage [v] out pin sink current [a] out pin high side voltage vs. source current 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 0.0 0.5 1.0 1.5 2.0 2.5 3.0 out pin voltage [v] out pin source current [a] error amplifier gain and phase vs. frequency -80 -60 -40 -20 0 20 40 60 80 frequency [hz] gain [db] -180 0 180 phase [deg] 100 1k 10k 100k 1m 10m
an-060e rev.1.0 jun-2010 15 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 8. description of each circuit 1 reference voltage circuit the circuit generates the reference voltage (vref) of 3.70v1% compensated in temperature from vcc voltage. this voltages start to output when the undervoltage lockout protection (uvlo) is cancelled, and they stabilize after the supply voltage (vcc) reaches up to approx. 4.0v or higher. the voltage (vref) outputs externally from ref pin, therefore, it can serve as a stabilized power source for reference voltage of error amplifier and maximum output duty setting or the like. the output current circuit should be within 1ma. (in case of v cc =8v to 28v should be within 7ma) the v ref voltage also is used as a regulated power supply for ic?s internal blocks. vref pin have to connect capacitors c ref for in order to stabilize voltages (to determine capacitance, refer to recommended operating conditions). 2 oscillator the oscillator generates triangular waveforms by charging and discharging the built-in capacitor. any desired oscillation frequency can be obtained by setting the value of the resistor connected to rt pin (fig. 1). the voltage oscillates between approximately 1.3v and 2.3v in charging and discharging with almost the same gradients (fig. 2). your desired oscillation frequency can be determined by changing the gradient using the resistor (rt) connected to rt pin. (large rt: low frequency, small rt: high frequency) the waveforms of oscillator cannot be observed from the outside because a pin for this purpose is not provided. approximately dc 1v is output to rt pin. the oscillator output is connected to pwm comparator. 3 error amplifier error amplifier has the inverting input in*(-) pin (pin7, pin20 and pin23) and non-inverted input in*(+) pin (pin6, pin21 and pin24) outputting externally, various circuit can be designed by kinds of external circuit structures. fb pins (pin, pin19 and pin22) are the outputs of error amplifiers. voltage gain and phase compensation can be set by connecting a capacitor (c) and a resistor (r) between fb pin and in*(-) pin.(fig. 3) for more information about the connection for each output voltage of power supply, refer to design advice. 4 pwm comparator the pwm output generates from the oscillator output, the error amplifier output (fb1, fb2 and fb3) and cs voltage (cs1, cs2 and cs3) (fig. 4). the oscillator output is co mpared with the preferred lower voltage between fb and cs for ch1 and ch3. while the preferred voltage is lower than oscillator output, the pwm output is lo w. while the preferred voltage is higher than oscillator output, the pwm output is high. since the phase of ch2 is the opposite phase of ch1 and ch3, higher voltage between fb2 and cs2 is preferred and while the preferred voltage is lower than the oscillator output, the pwm output 2 is high. (cannot be observed externally) the output duty changes sharply around the minimum and the maximum output duty. this phenomenon occurs more conspicuously when operating in a high frequency (i.e. when the pulse width is narrow). cautious care must be taken when using high frequency. the output polarity of out1, out2 changes according to the condition of sel pin. (see fig. 6) osc 2 rt r t fig.1 fig.2 2.3v 1.3v r t value:small r t value:lage fig.4 fb1 fb2 fb3 pwm comp.1 pwm comp.2 pw m comp.3 cs1 cs2 cs3 uvlo osc pch drive n/p ch drive n/p ch driv pw m output.1 pw m output.2 pwm output.3 12 13 5 15 3 out1 out2 sel2 out3 sel3 fig.3 6 7 8 21 20 19 er.amp1 er.amp2 24 23 22 er.amp3 4 in1- in1+ vref fb1 in2+ in2- fb2 in3+ in3- fb3 vout1 vout2 vout3 for pwm comparator for pwm comparator for pwm comparator
an-060e rev.1.0 jun-2010 16 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 5 soft start circuit this ic has a soft start function to protect dc-to-dc converter circuits from damage when starting operation. cs1 pin (pin11), cs2 pin (pin14) and cs3 pin (pin16) are used for soft start function of ch1, ch3 and ch2 respectively. (fig. 5) when the supply voltage is applied to the vcc pin and uvlo is cancelled, capacitor c cs1 , c cs2 and c cs3 is charged by vref through the resistor r cs1 , r cs2 or r cs3 . therefore, cs1 and cs3 voltage gradually increases and cs2 voltage gradually decreases. since cs1, cs2 and cs3 pin are connected to the pwm comparator internally, the pulses gradually widen and then the soft start function operates. (fig. 6) the maximum duty cycle can be set by using the cs pins. (see design advice about the detail) 6 timer latched short-circuit protection this ic has the timer latch short-circuit protection circuit. this circuit cuts off the output of all channels when the output voltage of dc-to-dc converter drops due to short circuit or overload. to set delay time for timer latch operation, a capacitor c cp should be connected to the cp pin (fig. 7). 1 cp c cp v cp i cp when one of the output voltage of the dc-to-dc converter drops due to short circuit or overload, the fb1 and fb3 pin voltage increases up to around the vref voltage for ch1 and ch3, or the fb2 pin voltage drops down to around 0 v for ch2. when fb1 and fb3 pin voltage exceeds 3.2v(max.) or fb2 pin voltage falls below 0.4v(min.), constant-current source (2.5 a typ.) starts charging the capacitor c cp connected to the cp pin. if the voltage of the cp pin exceeds 3.2 v (max.), the circuit regards the case as abnormal. then the ic is set to off latch mode and the output of all channels is shut off, (fig. 8) and the current consumption becom e 4ma(typ.) the period (tp) between the occurrence of short-circuit in the converter output and setting to off latch mode can be calculated by the following equation: cp on thcp cp i v c s tp = ] [ v thcpon : cp pin latched mode threshold voltage [v] i cp : cp charge source current[ a] c cp : capacitance of cp pin capacitor[ f] you can reset off latched mode of the short-circuit protection by either of the following ways about 1) cp pin, or 2) vcc pin: 1) cp voltage = 0v 2) vcc voltage uvlo voltage (3.3v, typ.) or below if the timer-latched mode is not necessary, connect the cp pin to gnd. fig.5 4 11 vref cs1 c cs1 r cs1 4 14 vref cs2 c cs2 r cs2 4 16 vref cs3 c cs3 r cs3 error amplifier 1,3 output oscillator output cs1 cs3 pin voltage pw m output 1 3 out1 out3 pch driven (sel3 vref) out3 nch driven (sel3 gnd) error amplifier 2 output oscillator output cs2 pin voltage pw m output 2 out2 pch driven (sel2 vref) out2 nch driven (sel2 gnd) fig.7 fig.8 1.0v 2.0v 3.0v cp pin voltage [v] time t 3.2v(max) start-up tp short circuit protection vref voltage short circuit momentary short circuit fig.6
an-060e rev.1.0 jun-2010 17 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 7 output circuit the ic contains a push-pull output stage and can directly drive mosfets. the maximum peak current of the output stage is sink current of +800ma, and source current of - 800ma. the ic can also drive npn and pnp transistors. the maximum current in such cases is 50ma. you must design the output current considering the ra ting of power dissipation. (see design advice) you can switch the types of external discrete mosfets by wiring of the sel pins (pin 3, pin 5). for driving nch mos, connect the sel pins to gnd. for driving pch mos, connect the sel pins to vref. you can design buck converter or inverting converter by driving pch mos, and boo st converter by driving nch mos. connect them either to gnd or to vref surely. 8 under voltage lockout circuit uvlo the ic contains a under voltage lockout circuit to protect the circuit from the damage caused by malfunctions when the supply voltage drops. when the supply voltage rises from 0v, the ic starts to operate at v cc of 3.3v(typ.) and outputs generate pulses. if a drop of the supply voltage occurs, it stops output at v cc of 3.2v(typ.). when it occurs, the cs1 and cs3 pin are turned to low level and the cs2 pin to high level, and then these pins are reset.
an-060e rev.1.0 jun-2010 18 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 9. design advice 1 setting the oscillation frequency as described at section 8-(2), ?description of each circuit,? a desired oscillation frequency can be determined by the value of the resistor connected to the rt pin. when designing an oscillation frequency, you can set any frequency between 200khz and 800khz. you can obtain the oscillation frequency from the characteristic curve ?oscillation frequency (fosc) vs. timing resistor resistance (r t )? or the value can be approximately calculated by the following expression. 105 . 1 3 905 . 0 3 10 1 . 4 10 1 . 4 ? ? ? ? ? ? ? ? = = ? fosc r r fosc t t fosc : oscillation frequency [khz] r t timing resistor [k ] this expression, however, can be used for rough calculation, the obtained value is not guaranteed. the operation frequency varies due to the conditions such as tolerance of the ch aracteristics of the ics, influence of noises, or external discrete components. when determining the values, examine the effectiveness of the values in an actual circuit. the timing resistor r t should be wired to the gnd pin as shortly as possible because the rt pin is a high impedance pin and is easy affected by noises. 2 determining soft start period the period from the start of charging the capacitor c cs to widening n% of output duty cycle can be roughly calculated by the following expression: (see fig. 5 for symbols) for cs1: ? ? ? ? ? ? ? ? ? = n cs ref ref cs cs v v v c r ms ts 1 1 1 1 ln ] [ for cs2 ? ? ? ? ? ? ? ? = n cs ref cs cs v v c r ms ts 2 2 2 2 ln ] [ for cs3 ? ? ? ? ? ? ? ? ? = n cs ref ref cs cs v v v c r ms ts 3 3 3 3 ln ] [ c cs1 ,c cs2 ,c cs3 : capacitance connected to cs* pin [ f] r cs1 ,r cs2 ,r cs3 : resistance connected to cs* pin [k ] v cs*n represents the voltage of cs pin in the output duty of n%, and it changes according to the operation frequency. the value is obtained simply from the chart of ?cs pin voltage vs. output duty cycle? characteristic curves. charging of cs pin begins after uvlo is cancelled. note that the time from power-on of power supply to start of charging ccs* is t0, which is not zero as described in fig. 8. be careful. to reset the soft start function, the voltage of cs pin is discharged with internal switch triggered by lowering the voltage of power supply below the voltage of uvlo (3.3v, typ.). if power supply restarts before the voltage is sufficiently discharged, the soft start function might not properly operate. accordingly, cautious care must be taken about it. 3 setting the maximum output duty if you need to control the maximum output duty in the dc-dc converter circuit, you can control pulse width by connecting vref pin to cs pin divided with resistors, as described in fig. 10. the output duty of the voltage of cs pin in this case changes according to the operation frequency, as described in the chart of ?cs pin voltage vs. duty cycle? characteristic curves. set the output duty accordingly based on your required operation frequency. when the maximum duty cycle is limited, cs pin voltage at start-up is described in fig. 11, and the approximate value of soft start period can be obtained by the following expressions: for cs1 ? ? ? ? ? ? ? ? ? = n cs cs cs cs v v v c r ms ts 1 1 1 1 0 1 ln ] [ 2 1 2 1 0 r r r r r + ? = ref cs v r r r v ? + = 2 1 2 1 for cs2 ? ? ? ? ? ? ? ? ? ? = 2 2 2 2 0 2 ln ] [ cs n cs cs ref cs v v v v c r ms ts 4 3 4 3 0 r r r r r + ? = ref cs v r r r v ? + = 4 3 3 2 fig.10 4 11 vref cs1 c cs1 r1 4 14 vref cs2 c cs2 r3 r2 r4 4 vref r5 16 cs3 r6 c cs3 fig.11 cs1,3 pin voltae v cs1n s v cs3n cs2 pin voltge v cs2n s r3 r3+r4 ? v ref r2 r1+r2 ? v ref r6 r5+r6 ? v ref fig.9 vcc cs pin voltage threshold voltge (3.3v typ.) v csn t0 ts
an-060e rev.1.0 jun-2010 19 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ for cs3 ? ? ? ? ? ? ? ? ? = n cs cs cs cs v v v c r ms ts 3 3 3 3 0 3 ln ] [ 6 5 6 5 0 r r r r r + ? = ref cs v r r r v ? + = 6 5 6 3 c cs1 ,c cs2 ,c cs3 : capacitance connected to cs* pin [ f] r1 to r6 : resistance connected to cs* pin [k ] the output duty changes sharply around the minimum and the maximum output duty. this phenomenon occurs more conspicuously when operating in a high frequency (i.e. when the pulse width is narrow). cautious care must be taken when using high frequency. 4 pull-up/pull-down resistor at the output section the power supply for control blocks of out pin drivers is the vref. the vref voltage is not operated at the condition of ic?s power supply vcc below the uvlo voltage. therefore, out* pins are unstable at vcc below the uvlo voltage. if you have this condition of vcc and possibility of some trouble by unstable out* pins, connect pull up or pull down resistor to out* pins. (fig.12) 5 restriction and recommended operating conditions of external discrete component to achieve a stable operation of the ic, the value of external discrete components connected to vcc, pvcc, vref, cs, cp pins should be within the recommended operating conditions. and the voltage and the current applied to each pin should be also within the recommended operating conditions. if the pin voltage of out1, out2, or vreg becomes higher than the vcc pin voltage, the current flows from the pins to the vcc pin because parasitic three diode exist between the vcc pin and these pins. be careful not to allow this current to flow. 6 performance of output stage the performance of output stages is the sink current (peak) of 800ma of and the source current (peak) of -800ma. switching speed is effected by external switching device, especially at high frequency, so examine the external switching device and frequency carefully. if the performance of the ics is not sufficient for your design, consider adding a buffer circuit to improve the performance. 7 loss calculation since it is difficult to measure ic loss directly, the calculation to obtain the approximate loss of the ic connected directly to a mosfet is described below. when the supply voltage is v cc , the current consumption of the ic is i ccop , the total input gate charge of the driven mosfet is qg and the switching frequency is fsw, the total loss pd of the ic can be calculated by: pd P v cc *(i ccop +qg*fsw). the value in this expression is influenced by the effects of the dependency of supply voltage, the characteristics of temperat ure, or the tolerance of parameter. therefore, evaluate the appropriateness of ic loss sufficiently considering the range of values of above parameters under all conditions. example) i ccop =7ma for v cc =12v in the case of a typical ic from the characteristics curve. qg=10nc, fsw=560khz, the ic loss ?pd? is as follows. pd P 12*(7ma+10nc*560khz) P 151mw if two mosfets are driven under the same condition for 3 channels, pd is as follows: pd P 12*{7ma+3*(10nc*560khz)}=286mw for pch driven for nch driven fig.12 ctrl v ref 10 17 pgnd pvcc out 18 vcc vin 9 gnd ctrl v ref 10 17 pgnd pvcc out 18 vcc vin 9 gnd
an-060e rev.1.0 jun-2010 20 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 8 attention for driving bipolar transistor if you use bipolar transistor as a switching device, connect resistor r b between base of transistor and out* pin, else there is a possibility of destroy the ic by over current because ou t* pin driver does not contain a current limit resistor. (fig.13) output current of out* pins are below 40ma (continuous). the connection of capacitor c b is effective for speed up the switching. 9 on/off control on/off control using cs pin is not available when timer latch function is enable. in order to carry out on/off control with cs pin, cp pin should be connected to gnd so that timer latch function will be disable as shown in fig.14. for ch.1 and ch.3, output pulses are disabled by lowering cs pin voltage around zero. ch.1 is controlled by cs1 pin and ch.3 is controlled by cs3. for ch.2, pulling up cs2 pin voltage to vref voltage disables output pulses. each channel will re-start operation with soft-start function when cs pin is opened. fig.15 shows on/off control method for ch.1 and ch.3 when timer latched short protection is used for all channels. please take care of that ch.2 is not suitable for on/off control, because the error amplifier of ch.2 sinks large current ( much larger than 2.7ma ) for high voltage of fb2 pin to stop switching of out2 pin. the calculation example of on/off circuit in fig.15 is as follows. vref -> cs1 maximum current ? ics1max ? = v ref / r 18 ( ex. 3.7v / 100k ohm = 37ua ) vref -> cs3 maximum current ? ics3max ? = v ref / r 38 ( ex. 3.7v / 100k ohm = 37ua ) error amp. output source current ? i sofb ? = 185ua ( typ. ) for fb1 pin and fb3 pin the base current ratio of q fb * and q cs * should be same as the collector current ratio for each channel. ( above case : collector current ratio = 185 / 37 = 5 -> base resistor ratio = r 56 / r 55 = r 53 / r 52 = 5 ) base resistor voltage drop should be larger than 300mv in order to obtain good sharing of base current for q fb * and q cs *. here, assuming h fe less than 100 of q**, each base current are over 1.85ua and over 0.37ua. if r 57 and r 58 values to flow current over ( 1.85 ua + 0.37 ua ) are designed and r 55 = r 52 = 200k ohm and r 56 = r 53 = 1m ohm are selected, base resistor voltage of r 52 , r 53 , r 55 and r 56 are over 370mv and these satisfy ? 300mv condition ?. therefore, this condition achieves normal transistor operation. resistance of r 57 and r 58 should be smaller than 20% of above condition in order to obtain small h fe of ? 20 ? which achieves low saturation voltage of q**. in this case, if vcc = 17v (min.) and voltage drop of r 57 and r 58 = vcc - 2v, r 57 or r 58 < 20% * (17v - 2v ) / (1.85 ua + 0.37 ua ) = 1.35 m ohm fig.13 10 17 pgnd pvcc out 18 vcc vin 9 gnd r b c b 10 17 pgnd pvcc out 18 vcc vin 9 gnd r b c b fig.14 4 11 vref cs1 c cs1 14 cs2 16 cs3 c cs3 c cs2 on/off ctrl ch1 ch3 ch2 1 cp timer latched short protection : not available
an-060e rev.1.0 jun-2010 21 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ fig.15 on/off circuit q a1 , q a3 : assuming base voltage as 0.9 v ( max. ), r 59 , r 60 , r 61 and r 62 should be designed so that the base current are larger than each collector current / 20. here, 20 means fully small h fe in order to obtain low saturation voltage of q a *. r 51 , r 54 : the voltage drop should be lower than 0.5 v at fb1 pin or fb3 pin to obtain 0% duty for on mode of q fb *. ex. r 51 * i sofb = 1k ohm * 185 ua = 0.185 v < 0.5 v FA7711V 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 cp rt sel3 vref sel2 in1+ in1- fb1 in3+ in3- fb3 in2+ in2- fb2 vcc pvcc 9 10 11 12 gnd pgnd cs1 out1 16 15 14 13 cs3 out3 cs2 out2 4.7k 4.7k 4.7n 4.7n cp 0.1uf rt 18k ref 2.2uf cs1 0.1uf cs3 0.1uf rcs1 100k rcs3 100k cv : 0. 1 u f ic1 r54 1k r56 1m r55 200k r51 1k r53 1m r52 200k r58 : 100k r57 : 100k r59:100k r60:10k ch3:1.2v / 0v ch1:1.2v / 0v r61:100k r62:10k q fb3 q cs3 q a3 q fb1 q cs1 q a1 3.7v 3.7v ex. 17v maximum source current : 185ua(typ.) maximum source current : 185ua(typ.) note : channel 2 to control out2 pin is not suitable for on/off control.
an-060e rev.1.0 jun-2010 22 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 10 setting of the output voltage of dc-dc converter figure 16,17,18 shows the ways to set each channel of the output voltage of dc-dc converter. ? applications for each channels ch1 buck, inverting ch2 buck, boost, inverting, fly-back ch3 buck, boost, inverting, fly-back in the case of a boost, a buck, or a fly-back circuit, the output voltage can be calculated with: for ch1 (fig.16,fig.17) 1 11 11 10 1 v r r r vout + = for ch2 (fig.17,fig.18) 2 21 21 20 2 v r r r vout + = for ch3 (fig.16,fig.18) 3 31 31 30 3 v r r r vout + = an inverting circuit, the output voltage can be calculated with: for ch1 (fig.18) ref v r r v r r r vout ? + = 10 11 1 10 11 10 1 for ch2 (fig.16) ref v r r v r r r vout ? + = 20 21 2 20 21 20 2 for ch3 (fig.17) ref v r r v r r r vout ? + = 30 31 3 30 31 30 3 the ratio of resistance can be calculated with: 1 1 1 11 10 v vout v v r r ref + ? = (use the absolute value of vout voltage) (the same vout2 and vout3 as vout1) vout1 vout2 vout3 4 24 vref 23 21 20 15 13 12 7 5 6 3 out1 out2 out3 er.amp1 er.amp2 er.amp3 sel3 sel2 8 19 22 vref * * vout1 vout2 vout3 vref in1+ in1- fb1 in2+ in2- fb2 in3+ in3- fb3 v1 r ref1 r ref2 r10 r11 r21 r20 r31 r30 v2 v3 vout1 vout2 vout3 4 24 vref 23 21 20 15 13 12 7 5 6 3 out1 out2 out3 er.amp1 er.amp2 er.amp3 sel3 sel2 8 19 22 vref vout1 vout2 vout3 vref in1+ in1- fb1 in2+ in2- fb2 in3+ in3- fb3 v1 r ref1 r ref2 r10 r11 r21 r20 r31 r30 vref r ref3 r ref4 r ref5 r ref6 v2 v3 vout1 vout2 vout3 4 24 vref 23 21 20 15 13 12 7 5 6 3 out1 out2 out3 er.amp1 er.amp2 er.amp3 sel3 sel2 8 19 22 vout1 vout2 vout3 vref in1+ in1- fb1 in2+ in2- fb2 in3+ in3- fb3 r10 r11 r21 r20 r31 r30 vref r ref1 r ref2 r ref3 r ref4 r ref5 r ref6 v1 v2 v3 fig.16 fig.17 fig.18
an-060e rev.1.0 jun-2010 23 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 11 protection from negative voltage apply if rather large negative voltage is applied to any pins of this ic, internal parasitic elements start operating, and they may cause malfunctions. accordingly, the negative voltage, which is applied to each pin of the ics, must be kept above -0.3v. in the case of the out* pin, in particular, the oscillation of voltage occurring after mosfet?s turning off can be applied to the out* pin through mosfet?s parasitic capacitance. as a result, there is a possibility that the negative voltage is applied to the out* pin. if this negative voltage reaches -0.3v or below, connect an schottky barrier diode between out* pin and gnd as shown in fig. 21. the schottky barrier diode?s forward direction voltage clamps the voltage applied to the out* pin. in this case, use the schottky barrier diode with low voltage drop in forward direction. other pins should be kept above -0.3 v also based on the same reasons. in the case of an inverting circuit, the negative voltage charged on the output capacitor will be applied to vref pin just after turning off the input voltage. if input voltage is turned on during applying a negative voltage to vref pin, the negative voltage may lead malfunction. this problem is likely to oc cur in the case of short interruption. in such a case, re-start the converter after the output capacitor is discharged enough or connect a schottky barrier diode with low forward voltage between vref pin and gnd as shown in fig.20. 10 17 pgnd pvcc out 18 vcc vin 9 gnd sbd 10 in- 9 out 4 in+ vref negative voltge sbd 12 an error pulse at start up at start up, if rise time of vcc and pvcc pin is too short, an error pulse, which is several tens s of width, may appear on the out pin. the internal circuit of ic is not stable before vref pin voltage rises to about 1v. therefore, it may cause an error pulses that a voltage is applied to pvcc pin before vreg pin voltage raises enough at start up. the error pulse may appear when vcc rise time from 0v to 12v is less than about a few hundred s. in such a case, check the influence of the error pulse such as blowout of a fuse. on the other hand, if rise time of vcc is not so short, the error pulse will not appear. vcc vref out(nch drive) about 1v 12v about a few hundredsec 13 design of phase compensation a switching power supply supervises output voltage with error amplifier, constitutes a closed loop, and is stabilizing voltage by negative feedback. phase delay with a smoothing filter and gain with the main switching device, etc. is contained in the negative feedback circuit, and those sum totals become the phase and the gain in a closed loop. the phase and the gain have the frequency characteristic. in a negative feedback circuit, if the gain remains 0db or more at the frequency of 180 degrees delayed phase, a circuit will be oscillated. in order to prevent oscilla tion, it is necessary to adjust the phase and the gain of error amplifier. (fig.22) since especially the switching power supply has repeated on and off at high speed, the minute high frequency element is contained in the output, and if you setup the frequency characteristic of the error amplifier beyond necessity, it has a possibility of unstable operate and oscillate. the gain when the phase turns 180 degrees calls gain margin, the phase when the gain becomes 0db calls phase margin. above 10db of gain margin and above 50 degrees of phase margin are desirable generally and set to this condition in phase compensation. (fig.22) however, gain margin and phase margin against transient response (sudden change of load, etc.) are participate as trade-off, therefore when gain margin and phase margin is larger, transient response becomes margin-less condition, furthermore over shoot and under shoot of converter voltage is larger. fig.19 fig.20 fig.21
an-060e rev.1.0 jun-2010 24 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ to determine the value of circuit components, it cannot decide here since conditions change a lot with the value of an output filter or others, but generally adjust the value between 1k and 100k of resistor r fb and the value between 1nf and 100nf of capacitor c fb . however the operation of switching power supply changes by l oad condition, duty cycle, temperature, etc., so wh en determine the value of components, examine with the real load condition in actual circuit. in- in+ fb vout r fb c fb gan phase 0db 180 0 gain margin phase margin 10db 50 dgree fig.22 fig.23
an-060e rev.1.0 jun-2010 25 FA7711V fuji electric systems co., ltd. http://www.fujielectric.co.jp/fdt/scd/ 10. application circuit FA7711V 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 cp rt sel3 vref sel2 in1+ in1- fb1 in3+ in3- fb3 in2+ in2- fb2 vcc pvcc 9 10 11 12 gnd pgnd cs1 out1 16 15 14 13 cs3 out3 cs2 out2 15v/800ma -10v/50ma 3.3v/300ma vin 8 14v sc802-04 0.022 f9.1k 1 f 33k 39k 10k 4700pf 20k 13k 100k 0.1 f 0.01 f 4.7k 10k 4700pf 1 f 2k 13k 5.1k 36k 0.1 f 150k 100k 150k 100k 0.1 f 4.7 h 22 h 47 h 33 f 4.7 f 22 f (os-con) 220 f sc802-04 sc802-04 obtained values are not guaranteed. when determining values and external discrete compo nents, examine under the actual circuit condition.

▲Up To Search▲

Price & Availability of FA7711V

	To Download FA7711V Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .